A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode over-lying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion;
(2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
A typical four transistor (4T) CMOS imager pixel 10 is shown in FIG. 1. The pixel 10 includes a photosensor 12 (e.g., photodiode, photogate, etc.), transfer transistor 14, floating diffusion region FD, reset transistor 16, source follower transistor 18 and row select transistor 20. The photosensor 12 is connected to the floating diffusion region FD by the transfer transistor 14 when the transfer transistor 14 is activated by a transfer gate control signal TX.
The reset transistor 16 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa_pix. A reset control signal RST is used to activate the reset transistor 16, which resets the floating diffusion region FD to the array pixel supply voltage Vaa_pix level as is known in the art.
The source follower transistor 18 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa_pix and the row select transistor 20. The source follower transistor 18 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal Vout. The row select transistor 20 is controllable by a row select signal SEL for selectively connecting the source follower transistor 18 and its output voltage signal Vout to a column line 22 of a pixel array.
The signals output from the pixel 10 are analog voltages representing a reset signal Vrst (generated when the floating diffusion region FD is reset) and a pixel output signal Vsig generated after charge from the photodiode 12 is transferred to the floating diffusion region FD. The output signals must be converted from analog to digital for further processing. Thus, the pixel output signals Vrst, Vsig are usually sent to a sample and hold circuit and then to a differencing circuit, which forms the signal Vrst-Vsig. This difference signal is then sent to an analog-to-digital converter (ADC) (not shown in FIG. 1). Many CMOS image sensors use a ramp analog-to-digital converter, which is essentially a comparator and associated control logic. In the conventional ramp analog-to-digital converter, an input voltage of the signal to be converted is compared with a gradually increasing reference voltage. The gradually increasing reference voltage is generated by a digital-to-analog converter (DAC) as it sequences through and converts digital codes into analog voltages. This gradually increasing reference voltage is known as the ramp voltage. In operation, when the ramp voltage reaches the value of the input voltage, the comparator generates a signal that latches the digital code of the DAC. The latched digital code is used as the output of the analog-to-digital converter.
In high resolution CMOS imaging applications, for example, column-parallel analog-to-digital converters are being increasingly used as the preferred method of converting the charge captured by the CMOS sensors to the digital outputs. The single-slope analog-to-digital conversion techniques employed so far have some benefits such as e.g., good linearity and simple implementation. This type of conversion, however, is slow and for analog-to-digital converters with a 12-bit or more resolution, higher performance is needed. In today's imagers where the resolution is approximately 4 mega-pixels or more, this becomes a major issue. Accordingly, there is a need and desire for higher performance analog-to-digital converters used in imagers.
To achieve high conversion rates, a modulating ramp analog-to-digital conversion technique has been proposed. This technique, however, requires complex square-root modulation to follow photon noise characteristics. Current ramp generators have a number of limitations and one of them is the non-programmability of the break points of the ramp curve. Accordingly, there is a need and desire for modulating ramp analog-to-digital converters that have programmable break points.
An advantage of the column-parallel analog-to-digital converter is its ability to have more than one mode of data conversion. This adds flexibility and performance and is achieved by changing the shape of the ramp. Currently, however, a multi-mode ramp generator that does not adversely impact the overall performance of the analog-to-digital converter has not been satisfactorily achieved. Accordingly, there is a need and desire for a multi-mode ramp generator that does not adversely impact the overall performance of the analog-to-digital converter.